The disclosure relates generally to input/output computer systems, and more particular, management of peripheral-component-interconnect (PCI) devices utilized in synchronous input/output computer systems.
A peripheral-component-interconnect (PCI) interface such as peripheral-component-interconnect express (PCIe), for example, may transfer data between main storage and the PCI function's storage by means of direct-memory-access (DMA) read/write requests. A DMA operation initiated by a PCI function may be targeted to one of several DMA address spaces in main storage. The PCI virtual address used by the DMA operation undergoes a dynamic address translation into an absolute address within the configuration to which the PCI function is attached. The I/O subsystem may provide a high-speed cache of past PCI address-translations, reducing the number of main-storage accesses needed to perform subsequent translations. Such a cache is generally referred to as a translation-lookaside buffer (TLB). During the life of a PCI DMA address space, translation parameters (e.g., region-table entries, segment-table entries, and page table entries) used by the PCI address-translation mechanism may need to be altered by the operating system. However, since the I/O subsystem may have cached translation parameters used in past translations, the operating system is required to purge any TLB entries corresponding to the altered translation table entries.
Whenever a PCI address with a different backing address is reused, the address range for the affected device must be purged in order to avoid reuse of stale AT entries. Conventional systems utilize firmware (i.e. software), which on each change in the mapping of PCI addresses, forces a purge of the PCI address translations associated with the device. However, latency and CPU cycles are consumed each time the firmware outputs the purge command, e.g., each time the firmware outputs a refresh PCI translation (RPCIT) millicode command.